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We present a novel architecture for the design of single-photon detecting arrays that captures relative intensity or timing information from a scene, rather than absolute. The proposed method for capturing relative information between pixels or groups of pixels requires very little circuitry, and thus allows for a significantly higher pixel packing factor than is possible with per-pixel TDC approaches. The inherently compressive nature of the differential measurements also reduces data throughput and lends itself to physical implementations of compressed sensing, such as Haar wavelets. We demonstrate this technique for HDR imaging and LiDAR, and describe possible future applications.

 

Van der Waals (vdW) ferroelectrics have attracted significant attention for their potential in next-generation nano-electronics. Two-dimensional (2D) group-IV monochalcogenides have emerged as a promising candidate due to their strong room temperature in-plane polarization down to a monolayer limit. However, their polarization is strongly coupled with the lattice strain and stacking orders, which impact their electronic properties. Here, we utilize four-dimensional scanning transmission electron microscopy (4D-STEM) to simultaneously probe the in-plane strain and out-of-plane stacking in vdW SnSe. Specifically, we observe large lattice strain up to 4% with a gradient across ~50 nm to compensate lattice mismatch at domain walls, mitigating defects initiation. Additionally, we discover the unusual ferroelectric-to-antiferroelectric domain walls stabilized by vdW force and may lead to anisotropic nonlinear optical responses. Our findings provide a comprehensive understanding of in-plane and out-of-plane structures affecting domain properties in vdW SnSe, laying the foundation for domain wall engineering in vdW ferroelectrics.

 

Memristors are promising candidates for constructing neural networks. However, their dissimilar working mechanism to that of the addressing transistors can result in a scaling mismatch, which may hinder efficient integration. Here, we demonstrate two-terminal MoS2 memristors that work with a charge-based mechanism similar to that in transistors, which enables the homogeneous integration with MoS2 transistors to realize one-transistor-one-memristor addressable cells for assembling programmable network. The homogenously integrated cells are implemented in a 2×2 network array to demonstrate the enabled addressability and programmability. The potential for assembling scalable network is evaluated in a simulated neural network using obtained realistic device parameters, which achieves over 91% pattern recognition accuracy. This study also reveals a generic mechanism and strategy that can be applied to other semiconducting devices for the engineering and homogeneous integration of memristive systems. 

Programmers often rely on online resources—such as code examples, documentation, blogs, and Q&A forums—to compare similar libraries and select the one most suitable for their own tasks and contexts. However, this comparison task is often done in an ad-hoc manner, which may result in suboptimal choices. Inspired by Analogical Learning and Variation Theory, we hypothesize that rendering many concept-annotated code examples from different libraries side-by-side can help programmers (1) develop a more comprehensive understanding of the libraries’ similarities and distinctions and (2) make more robust, appropriate library selections. We designed a novel interactive interface, ParaLib, and used it as a technical probe to explore to what extent many side-by-side concepted-annotated examples can facilitate the library comparison and selection process. A within-subjects user study with 20 programmers shows that, when using ParaLib, participants made more consistent, suitable library selections and provided more comprehensive summaries of libraries’ similarities and differences.